Semiconductor device having reduced sub-threshold leakage

ABSTRACT

A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor.

TECHNICAL FIELD

This invention relates generally to integrated circuit devices, and,more particularly, to improved vertical transistor structures and amethod of making such transistor structures.

BACKGROUND OF THE INVENTION

Conventional semiconductor electronic storage devices, such as DynamicRandom Access Memory (“DRAM”) devices, typically incorporate capacitorand transistor structures in which memory cell capacitors temporarilystore data based on the charged state of the capacitors. When data bitsare to be written to or read from the memory cells, the memory cellcapacitors are selectively coupled to digit lines through respectiveaccess transistors.

There is an ever-present desire in the semiconductor fabricationindustry, in general, and the memory industry, specifically, to achieveindividual devices with smaller physical dimensions. Reducing thedimensions, a process known as “scaling,” is desirable in order toincrease the number of individual devices that can be placed on a givenarea of semiconductor material thereby reducing the unit cost and thepower consumption of individual devices. In addition, scaling can resultin performance increases of the individual devices as the chargecarriers, having a finite velocity, have a shorter distance to travel,and they provide less bulk material for charge to accumulate ordissipate.

One method of designing smaller memory cells is to use verticaltransistors, such as fin field effect transistor (“FinFET”) devices. AFinFET device employs a vertically arranged structure or fin interposedbetween the source and drain where the channel is defined, typicallywith a multi-gate configuration. The advantages of the FinFETarchitecture include the ability to define device dimensions smallerthan the photolithographic limit and the ability to easily accessopposed sides of the channel to achieve a multi-gate structure. Such amulti-gate arrangement can provide superior control over the gate of thedevice. A fully depleted silicon fin can be achieved with very lowdoping levels in the active region.

With reference to FIG. 1, a FinFET device 10 typically includes a fin 14extending between a vertically oriented drain pillar 18 and a verticallyoriented source pillar 20. The fin 14, drain pillar 18 and source pillar20 are fabricated in a body 22 of semiconductor material. Gates 24 arefabricated on each side of the fin 14, although only one gate 24 isshown in FIG. 1.

A prior art structure for using FinFET devices 10 used as a DRAM accesstransistor is shown in FIG. 2. The drain pillar 18 is common to twoFinFET devices 30, 32. The source pillar 20 of the first FinFET device30 is separated from the source pillar 20 of a third FinFET device 36through a shallow trench isolation (STI”) structure 40 fabricated in thebody 22. The STI structure 40 electrically isolates the source pillar 20of the FinFET device 30 from the source pillar 20 of the FinFET device36. Similarly, the source pillar 20 of the second FinFET device 32 isisolated from the source pillar 20 of a fourth FinFET device 44 by a STIstructure 48. The drain pillar 18 is common to two FinFET devices 30,32, and it is connected to a common digit line 26. The source pillars 20of the FinFET devices 30, 32, 36, 44 are connected to respective memorycell capacitors 28.

Although scaling memory devices, such as DRAMs, provide the advantagesof reducing cost and power consumption, scaling is not without itsperformance drawbacks. In particular, scaling can increase sub-thresholdleakage between the drain pillar 18 and source pillar 20. In someapplications, sub-threshold leakage does not present any problems in theuse of FinFET devices. However, in other applications, such as for useas access transistors, sub-threshold leakage can significantly degradethe performance of DRAM devices. The length of time that memory cellcapacitors can store charge is greatly effected by the amount ofsub-threshold leakage through the respective access transistors to whichthey are connected. Shorter charge retention times require that thememory cells be refreshed more frequently. However, refreshing memorycells consumes a significant amount of power. Therefore, excessivesub-threshold leakage of access transistors can greatly increase theamount of power consumed by DRAM devices. Furthermore, if thesub-threshold leakage is large enough, it can result in data retentionerrors.

A primary cause of sub-threshold leakage in FinFET devices arises fromthe structure that is typically used for FinFET devices. In particular,the fin 14 is connected to the body 22 of semiconductor material inwhich the FinFET device 10 is fabricated, which can serve as a currentleakage path from a memory cell capacitor connected to the source pillar20. This current leakage path can seriously limit the use of FinFETdevices 10 for DRAM access transistors. There can also be sub-thresholdleakage from the source pillar 20 directly to the body 22 and from thedrain pillar 18 directly to the body. However, this leakage is of alesser magnitude and is thus less of a problem than leakage from the fin14 to the body 22.

There is therefore a need for a FinFET structure that reduces thesub-threshold leakage of FinFET devices, particularly between the finand body of such devices.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an isometric view of a prior art FinFet device.

FIG. 2 is cross-sectional view showing a prior art structure for usingFinFET devices as access transistors in dynamic random access memorydevices.

FIG. 3 is cross-sectional view showing a structure for using FinFETdevices as access transistors in dynamic random access memory devicesaccording to one embodiment of the invention.

FIG. 4 is a cross-sectional view of a FinFET device according to anotherembodiment of the invention.

FIG. 5 is a cross-sectional view of the FinFET device of FIG. 4 takenalong the line 5-5 of FIG. 4.

FIG. 6 is a flow chart showing one embodiment of a process forfabricating the semiconductor structures of FIGS. 3-5 or a semiconductorstructure according to some other embodiment of the invention.

DETAILED DESCRIPTION

One embodiment of a semiconductor structure 50 using two FinFET devices52, 54 for connecting respective memory cell capacitors (not shown) to adigit line (not shown) is shown in FIG. 3. The FinFET devices 52, 54,like the FinFET devices 30, 32 shown in FIG. 2, have fabricated on abody 58 of semiconductor material a common drain pillar 60 connected torespective source pillars 62 through respective fins 64. The drainpillar 60 is connected to a digit line conductor 66, and the sourcepillars 62 are connected to respective memory cell capacitors 68. TheFinFET devices 52, 54 also include shallow isolation trenches 74separating the source pillars 62 of the FinFET devices 52, 54 from thesource pillars 62 of adjacent FinFET devices 70, 72, respectively.

The drain pillar 60 is connected to a common digit line 66. The sourcepillars 62 of the FinFET devices 52, 54, 70, 72 are connected torespective memory cell capacitors 68. Unlike the STI structures 40 usedin the prior art structure of FIG. 2, the isolation trenches 74 havinglaterally extending cavities 80 formed therein. The cavities 80 extendunder the source pillars 62 of the FinFET devices 52, 54, 70, 72.Cavities 86 are also formed under the fins 64 of the FinFET devices 52,54, 70, 72.

The cavities 80, 86 reduce the size of any possible conduction path fromthe fins 64 to the body 58, and they also reduce the size of anypossible conduction path from the source pillars 62 to the body 58.These reductions in the size of any possible conduction paths have theeffect of increasing the resistance between the fins 64 and sourcepillars 62 to the body 58. As a result, the sub-threshold leakage of theFinFET devices 52, 54, 70, 72 are substantially reduced. The FinFETdevices 52, 54, 70, 72 are therefore better able to serve as DRAM accesstransistors.

Another embodiment of a semiconductor structure 100 using FinFET devicesis shown in FIGS. 4 and 5. FIG. 4 shows several FinFET devices 102, 104,106, 108 in the same orientation in which the FinFET devices 52, 54, 70,72 are shown in the structure 50 of FIG. 3. FIG. 5 shows thesemiconductor structure 100 taken along the line 5-5 of FIG. 4 in whichthe FinFET device 106 is shown in end view along with end views ofadjacent rows of FinFET devices 110, 112, 114, 116, 118. Each of theFinFET devices 102-108 and 110-118 includes a fin 130 extending betweena drain pillar 132 and a source pillar 134, all of which are fabricatedin a body 140 of semiconductor material. Unlike the FinFET devices 52,54, 70, 72 of FIG. 3, the drain pillars 132 are not shared by two FinFETdevices.

The FinFET devices 102-108 and 110-118 are electrically isolated fromeach other by a first STI structure 150 (FIG. 4) extending in onedirection and a second STI structure 152 (FIG. 5) extending in anorthogonal direction. However, in some embodiments, a single STIstructure can extend entirely around the fins 130, drain pillars 132 andsource pillars 134 so that the body 140 forms an upwardly projectingpedestal. In either case, a cavity 160 extends laterally from the STIstructures 150, 152 partially beneath the fins 130, drain pillars 132and source pillars 134. As explained above, the cavities 160 reduce inthe size of any possible conduction paths and thus increase theresistance between the fins 130, drain pillars 132 and source pillars134 to the body 140.

The semiconductor structures 50, 100 may be fabricated using a varietyof methods. One embodiment of a process 200 for fabricating thesemiconductor structures 50, 100 is shown in FIG. 6. The process 200first includes anisotropically etching the STI structures 74 and 150,152 at step 204 to a level that is approximately equal to the upper edgeof the cavities 80, 160. This step 204 forms relatively smooth walltrenches of relatively constant width. During the etching process,silicon dioxide SiO₂ is formed on the wall of the trenches. The SiO₂ isleft on the walls of the trench, but the SiO₂ is preferably removed fromthe bottom of the trenches at step 206. The SiO₂ is left on the walls ofthe trench for the next step 208 to serve as a mask. During this nextstep 208, the cavities 80, 160 are formed by isotropic etching. The SiO₂mask on the walls of the trench protect them from further etching, butthe bottom of the trench is etched in an isotropic manner to form thecavities 80, 160. The trenches are anisotropically etched again at step210 to form the portions of the STI structures 74, 150 extending beyondthe cavities 80, 160, respectively. Finally, trenches are filled in withSiO₂ by conventional means at step 214. The remaining structures of theFinFET devices, including the fins, are then subsequently fabricated byconventional means.

From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention. Accordingly, the invention is notlimited except as by the appended claims.

1. A semiconductor device comprising: a semiconductor substrate; opposedsource and drain pillars fabricated in the semiconductor substrate; afin fabricated in the semiconductor substrate and interposed between thesource and drain pillars; and a cavity formed in the semiconductorsubstrate, the cavity extending at least partially between the fin andthe semiconductor substrate.
 2. The semiconductor device of claim 1wherein the cavity further extends at least partially beneath at leastone of the source pillar and the drain pillar.
 3. The semiconductordevice of claim 2 wherein the cavity extends continuously around the finand the source and drain pillars.
 4. The semiconductor device of claim 1wherein the cavity extends at least partially between the fin and thesemiconductor substrate at opposite sides of the fin.
 5. A semiconductordevice comprising: a semiconductor substrate; opposed source and drainpillars fabricated in the semiconductor substrate; a fin fabricated inthe semiconductor substrate and interposed between the source and drainpillars; and a cavity formed in the semiconductor substrate extending atleast partially beneath at least one of the source pillar and the drainpillar.
 6. A semiconductor device for use as an access transistor in adynamic random access memory, the semiconductor device comprising: asemiconductor substrate; a first pillars fabricated in the semiconductorsubstrate and coupled to a digit line; a second pillar fabricated in thesemiconductor substrate and coupled to a first memory cell capacitor; afirst fin fabricated in the semiconductor substrate and interposedbetween the first pillar and the second pillar; a first cavity formed inthe semiconductor substrate, the first cavity extending at leastpartially between the first fin and the semiconductor substrate; a thirdpillar fabricated in the semiconductor substrate and coupled to a secondmemory cell capacitor; a second fin fabricated in the semiconductorsubstrate and interposed between the first pillar and the third pillar;and a second cavity formed in the semiconductor substrate, the secondcavity extending at least partially between the second fin and thesemiconductor substrate.
 7. The semiconductor device of claim 6 whereinthe first cavity extends at least partially beneath the second pillar,and the second cavity extends at least partially beneath the thirdpillar.
 8. The semiconductor device of claim 6 wherein the first cavityextends at least partially between the first fin and the semiconductorsubstrate at opposite sides of the first fin, and the second cavityextends at least partially between the second fin and the semiconductorsubstrate at opposite sides of the second fin.
 9. A semiconductor devicefor use as an access transistor in a dynamic random access memory, thesemiconductor device comprising: a semiconductor substrate; a firstpillars fabricated in the semiconductor substrate and coupled to a digitline; a second pillar fabricated in the semiconductor substrate andcoupled to a first memory cell capacitor; a first fin fabricated in thesemiconductor substrate and interposed between the first pillar and thesecond pillar; a first cavity formed in the semiconductor substrate, thefirst cavity extending at least partially beneath the second pillar;between the first fin and the semiconductor substrate; a third pillarfabricated in the semiconductor substrate and coupled to a second memorycell capacitor; a second fin fabricated in the semiconductor substrateand interposed between the first pillar and the third pillar; and asecond cavity formed in the semiconductor substrate, the second cavityextending at least partially beneath the third pillar.
 10. A method offabricating a pair of access devices for a dynamic random access memorydevice, the method comprising: fabricating a pair of FinFET devices on asemiconductor substrate, the FinFet devices having a common digit linepillar, respective memory cells pillars and respective fins extendingbetween the command digit line pillar and respective ones of the memorycell pillars; anisotropically etching the semiconductor substrate toform a shallow trench isolation structures adjacent at least the fins;and isotropically etching the semiconductor substrate within the shallowtrench isolation structures to form respective cavities in thesemiconductor structure extending from respective ones of the shallowtrench isolation structures at least partially beneath at least therespective fins.
 11. The method of claim 10, further comprising:anisotropically etching the semiconductor substrate to form respectiveshallow trench isolation structures adjacent the memory cell pillars;and isotropically etching the semiconductor substrate within the shallowtrench isolation structures adjacent the memory cell pillars to formrespective cavities in the semiconductor structure extending from theshallow trench isolation structures at least partially beneath at leastthe respective fins.
 12. The method of claim 10 wherein the methodfurther comprises, after isotropically etching the semiconductorsubstrate, anisotropically etching the semiconductor substrate withinthe shallow trench isolation structures to form respective extensions ofthe shallow trench isolation structures further into the semiconductorstructure.
 13. The method of claim 10, further comprising filling theshallow trench isolation structures and the cavities with silicondioxide.
 14. The method of claim 10 wherein the act of anisotropicallyetching the semiconductor substrate forms silicon dioxide on thesurfaces of the shallow trench isolation structures, and wherein themethod further comprises, prior to isotropically etching thesemiconductor substrate within the shallow trench isolation structures,removing the silicon dioxide from walls of the shallow trench isolationstructures but not from a bottom of the shallow trench isolationstructures so that the silicon dioxide left on the walls of the shallowtrench isolation structures form a protective mask on the walls but notthe bottom of the shallow trench isolation structures during theisotropic etching.
 15. The method of claim 10 wherein: the act ofanisotropically etching the semiconductor substrate comprisesanisotropically etching the semiconductor substrate adjacent oppositesides of the fins to form shallow trench isolation structures adjacentopposite sides of the fins, and the act of isotropically etching thesemiconductor substrate comprises isotropically etching thesemiconductor substrate within the shallow trench isolation structuresadjacent opposite sides of the fins to form respective cavities in thesemiconductor cavity adjacent opposite sides of the fins.
 16. The methodof claim 10 wherein: the act of anisotropically etching thesemiconductor substrate comprises anisotropically etching thesemiconductor substrate continuously around the fins and the memory cellpillars to form continuous shallow trench isolation structures extendingaround the respective fins and memory cell pillars; and the act ofisotropically etching the semiconductor substrate comprisesisotropically etching the semiconductor substrate within the shallowtrench isolation structures extending around the respective fins andmemory cells pillars to form respective cavities in the semiconductorsubstrate extending around the respective fins and memory cells pillars.17. A method of fabricating a semiconductor device on a semiconductorsubstrate, the method comprising: fabricating a FinFET device in thesemiconductor substrate having first and second pillars and a finextending therebetween; anisotropically etching the semiconductorsubstrate to form a shallow trench isolation structure adjacent at leastone of the first pillar, the second pillar and the fin; andisotropically etching the semiconductor substrate within at least aportion of the shallow trench isolation structure to form a cavity inthe semiconductor structure extending from the shallow trench isolationstructure beneath at least one of the first pillar, the second pillarand the fin.
 18. The method of claim 17, further comprising, afterisotropically etching the semiconductor substrate, anisotropicallyetching the semiconductor substrate within the shallow trench isolationstructure to form an extension of the shallow trench isolation structurefurther into the semiconductor structure.
 19. The method of claim 17wherein the act of anisotropically etching the semiconductor substrateforms silicon dioxide on the surfaces of the shallow trench isolationstructure, and wherein the method further comprises, prior toisotropically etching the semiconductor substrate within the shallowtrench isolation structure, removing the silicon dioxide from walls ofthe shallow trench isolation structure but not from a bottom of theshallow trench isolation structure so that the silicon dioxide left onthe walls of the shallow trench isolation structure forms a protectivemask on the walls but not the bottom of the shallow trench isolationstructure during the isotropic etching.
 20. The method of claim 17wherein: the act of anisotropically etching the semiconductor substratecomprises anisotropically etching the semiconductor substrate adjacentthe fin to form a shallow trench isolation structure adjacent the fin;and the act of isotropically etching the semiconductor substratecomprises isotropically etching the semiconductor substrate within theshallow trench isolation structure adjacent the fin to form a cavity inthe semiconductor cavity adjacent the fin.
 21. The method of claim 20wherein: the act of anisotropically etching the semiconductor substratecomprises anisotropically etching the semiconductor substrate adjacentopposite sides of the fin to form a shallow trench isolation structureadjacent opposite sides of the fin; and isotropically etching thesemiconductor substrate within the shallow trench isolation structureadjacent opposite sides of the fin to form a cavity in the semiconductorcavity adjacent opposite sides of the fin.
 22. The method of claim 21wherein: the act of anisotropically etching the semiconductor substratecomprises anisotropically etching the semiconductor substrate adjacentthe first pillar form a shallow trench isolation structure adjacent thefin and the first pillar; and the act of isotropically etching thesemiconductor substrate further comprises isotropically etching thesemiconductor substrate within the shallow trench isolation structureadjacent the fin and the first pillar to form a cavity in thesemiconductor cavity adjacent the fin and the first pillar.
 23. Themethod of claim 22 wherein: the act of anisotropically etching thesemiconductor substrate comprises anisotropically etching thesemiconductor substrate continuously around the fin, the first pillarand the second pillar to form a continuous shallow trench isolationstructure extending around the fin and the first and second pillars; andthe act of isotropically etching the semiconductor substrate comprisesisotropically etching the semiconductor substrate within the continuousshallow trench isolation structure to form a continuous cavity extendingaround the fin and the first and second pillars.
 24. The method of claim17, further comprising filling the shallow trench isolation structureand the cavity with silicon dioxide.